The present invention relates generally to static random access memories (SRAM), and more particularly to a circuit implementation for providing various voltages to an SRAM core array, depending on the mode of operation.
SRAM devices are used in a wide variety of applications. SRAM devices provide one or more randomly accessible memory array where the data contents can be written and re-written at any time. FIG. 1 shows a schematic of a conventional SRAM cell 100 that includes six transistors. A cross-coupled inverter pair, which is constructed by transistors 102, 104, 106, 108, and access transistors 110, 112 make up the SRAM cell 100. A supply voltage VCC powers the SRAM cell 100. The SRAM periphery power supply voltage (VDD) powers the word line (WL), bit line (BL) and complementary bit line (BLB). During write operation, a write data state is set by forcing complimentary voltages (0 and 1) on the BL and BLB, and forcing a high signal on WL to turn on the access transistors 110 and 112. This allows the data state to be forced into the cross-coupled inverter pair. The access transistors 110 and 112 are then turned off. The positive feedback of the cross-coupled inverter pair will ensure that the new data state is maintained. Typically, a plurality of memory cells is implemented on the SRAM device to form a large array of SRAM memory cells 100 powered by one supply voltage.
As the process used for semiconductor manufacturing moves towards the 0.13 um generation, the design rules continue to shrink for high density and high performance SRAM devices. As a result, the supply voltage VCC, of these devices must be reduced to below 1.0V. However, as the supply voltage VCC is reduced to below 1.0V, static noise margin (SNM) gets adversely affected, thereby leading to cell instability. SNM is defined as the minimum noise voltage at the cell storage nodes that is needed to flip the state of the cell. One method to improve SNM is by increasing the beta-ratio (β) of the SRAM cell. Beta-ratio (β) is the ratio of the width of the pull-down transistor to the access transistor. Increasing “beta-ratio” results in larger cell size of SRAM and hence is not desirable. Another method to improve SNM is by increasing the voltage supplied to the SRAM core array. Increasing the voltage supplied to the SRAM core array improves the SNM during read operation, but has an adverse effect on the write margin (WTM) during the write operation. While using two power supplies producing two different voltages, one for read and another for write operation, can improve both SNM and WTM, it makes the SRAM design more complex.
As such, what is needed is a single dynamic power supply for an SRAM core array that can provide multiple voltages during multiple operation modes such that the SNM and WTM issues can be addressed.